Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication

Reconfigurable computing brings immense flexibility to on-chip processing while network-on-chip has improved flexibility in on-chip communication. Integrating these two areas of research reaps the benefits of both and represents the promising future of multiprocessor systems-on-chip.

Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication is the one of the first compilations written to demonstrate this future for network -on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, this book represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.

The many academic areas covered in this publication include, but are not limited to:

• Administration of Reconfigurable NoCs
• Leveraging reconfiguration techniques
• Low-power network-on-chip
• Network-on-chip design flow
• NoC-based Infrastructures
• Operating system design
• Programming models for the processing elements
• Reconfigurable computing techniques
• Reconfiguring the Network-on-Chip processing elements
• Task Scheduling