Design and Test Technology for Dependable Systems-on-Chip
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Design and Test Technology for Dependable Systems-on-Chip

Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus
Release Date: December, 2010|Copyright: © 2011 |Pages: 578
DOI: 10.4018/978-1-60960-212-3
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
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Description & Coverage
Description:

Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined “classical” design and test topics and solutions for IC test technology and fault-tolerant systems.

Coverage:

The many academic areas covered in this publication include, but are not limited to:

  • Built-in self repair for logic structures
  • Combined test-data compression and test planning
  • Diagnostic modeling of digital systems
  • Fault simulation and fault injection technology
  • Fault-tolerant and fail-safe design based on reconfiguration
  • Flexible fault-tolerant schedules for embedded systems
  • Memory testing and self-repair
  • Optimizing fault tolerance for multi-processor system-on-chip
  • Software-based self-test of embedded microprocessors
  • Transient faults detection and compensation
Reviews & Statements

The book Design and Test Technology for Dependendable Embedded Systems presents stimulating new ideas and solutions for the design and test of realiable embedded systems.
It is written by successful academic researchers mainly from European universities. It inspires researchers, PhD- and Master-students in their own work in this challenging area. It gives fresh inputs to the development of new tools for the design and test of reliable systems built from unreliable components. The book deserves many readers both from academia and industry, and personally I wish the book great success.

– Prof. Michael Goessel, University of Potsdam, Germany
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Editor/Author Biographies
Raimund Ubar is a professor of computer engineering at Tallinn Technical University and the head of Centre of Excellence for Integrated Electronic Systems and Biomedical Engineering in Estonia. R. Ubar received his PhD degree in 1971 at the Bauman Technical University in Moscow. His main research interests include computer science, electronics design, digital test, diagnostics and fault-tolerance. He has published more than 250 papers and three books, lectured as a visiting professor in more than 25 universities in about 10 countries, and served as a General Chairman for 10th European Test Conference, NORCHIP, BEC, EWDTC. He is a member of Estonian Academy of Sciences, Golden Core member of IEEE Computer Society and honorary professor of National University of Radioelectronics Charkiv (Ukraine). He was a chairman of Estonian Science Foundation, and a member of the Academic Advisory Board of the Estonian President.
Jaan Raik received his M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology (TUT) in 1997 and in 2001, respectively. Since 2002 he holds a position of senior research fellow at TUT. He is a member of IEEE Computer Society, a Steering Committee member of European Dependable Computing Conference and Programme Committee member for many leading conferences (DATE, ETS, DDECS, etc.). Dr. Raik has co-authored more than 100 scientific publications. In 2004, he was awarded the national Young Scientist Award. In 2005, he served as the Organisation Chair of the IEEE European Test Symposium. He has carried out research work at several foreign institutes including Darmstadt University of Technology, INPG Grenoble, Nara Institute of Science and Technology (Japan), Fraunhofer Institute of Integrated Circuits (Dresden), University of Stuttgart and University of Verona. His main research interests include high-level test generation, fault tolerant design and verification. Dr. Raik was the local project lead for the VERTIGO FP6 STREP project on verification and is the coordinator of the DIAMOND FP7 STREP project.
Heinrich Theodor Vierhaus received a diploma degree in electrical engineering from Ruhr-University Bochum (Germany) in 1975. From 1975 to 1977 he was with the German Volunteer Service (DED/ GVS), teaching electronic and RF engineering courses at the Dar-es-Salaam Technical College in Tanzania (East Africa). Later he became a research assistant at the University of Siegen Germany), where he received a doctorate (Dr.- Ing.) in microelectronics in 1983. From 1983 to 1996 he was a senior researcher with GMD, the German national research institute for information technology at St. Augustin near Bonn, where he became the acting director of the System Design Technology Institute (SET) in 1993. During this time he also served as a part-time lecturer for the University of Bonn and Darmstadt University of Technology. Since 1996 he has been a full professor for computer engineering at Brandenburg University of Technology Cottbus. He has authored or co-authored more than 100 papers in the area of IC design and test technology. He has been a member of the IEEE for about 30 years.
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Editorial Advisory Board
  • Rolf Drechsler, University of Bremen, Germany
  • Elena Gramatová, Slovak University of Technology, Slovakia
  • Erik Larsson, Linköping University, Sweden
  • Ondrej Novák, Technical University Liberec, Czech Republic
  • Zebo Peng, Linköping University, Sweden
  • Matteo Sonza Reorda, Politecnico di Torino, Italy
  • Andreas Steininger, Vienna University of Technology, Austria